(1) Field of the Invention
The present invention relates to fabrication procedures used to create semiconductor devices, and more specifically to a process used to integrate the fabrication of a DRAM, metal capacitor structure, with some of the fabrication procedures used for logic devices.
(2) Description of Prior Art
Advanced semiconductor chips, now being manufactured in industry, are composed of logic or memory devices. Logic devices are used to process information or data, while memory devices are used for data storage. These two types of devices can be found in almost all computers, however they are usually found on specific chips, reserved for either logic or memory applications. In systems in which logic and memory devices are packaged separately, data signals between the two may have to pass through several levels of packaging, which can result in undesirable propagation delays. In addition the manufacturing costs for fabricating wafers producing only logic chips, and wafers with only memory chips, are greater than if both logic and memory applications can be incorporated on the same chip. Therefore for performance and cost reasons the semiconductor industry has been motivated to produce a semiconductor chip with both the desired logic and memory requirements.
This invention will describe a novel process sequence for forming a capacitor structure, for a dynamic random access memory, (DRAM), cell, while simultaneously fabricating the DRAM bit line structure, and simultaneously forming specific elements for adjacent logic devices. The use of shared process sequences, for both memory and logic devices, on the same semiconductor chip, increase the performance of both the logic and memory devices, while still reducing processing costs. The key feature of this invention is the formation of a metal storage node structure, for the DRAM capacitor, located over a bit line structure, fabricated simultaneously with the formation of the DRAM bit line structure, and with some of the wiring levels, used for the logic devices. The use of a low resistivity metal, for the storage node of the capacitor, allows this material, and process sequence, to be simultaneously used for high conductivity wiring levels, needed for adjacent logic devices. Prior art, such as Koh et al, in U.S. Pat. No. 5,627,095, describe a capacitor structure, formed over a bit line structure, however this prior art uses a polysilicon capacitor structure, not compatible, in terms of conductivity, with the needs of logic devices.